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november 2012 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator features ? 3 a output current ? over 95% efficiency ? fully synchronous operation with integrated schottky diode on low-side mosfet boosts efficiency ? programmable frequency operation (200 khz to 600 khz) ? power-good signal ? accepts ceramic capacitors on output ? external compensation for flexible design ? wide input range: 3 v to 24 v ? output voltage range: 0.8 v to 90%v in ? input under-voltage lockout ? programmable over-current limit ? under-voltage, over-voltage, and thermal protections ? 5x6 mm, 25-pin, 3-pad mlp applications ? graphics cards ? battery-powered equipment ? set-top boxes ? point-of-load regulation ? servers description the fan2103 tinybuck? is an easy-to-use, cost- and space-efficient, 3 a synchronous buck solution. it enables designers to solve high current requirements in a small area with minimal external components. external compensation, programmable switching frequency, and current limit f eatures allow for design optimization and flexibility. the summing current mode modulator uses lossless current sensing for current feedback and over-current, and includes voltage feedforward. fairchild?s advanced bicmos power process, combined with low r ds(on) internal mosfets and a thermally efficient mlp package provide the ability to dissipate high power in a small package. output over-voltage, under-voltage, and thermal shutdown protections plus power-good, help protect the devices from damage during fault conditions. related application notes ? tinycalc? design tool ? an-6033 ? tinycalc? design tool guide ? an-5067 ? pcb land pattern design and surface mount guidelines for mlp packages ordering information part number operating temperature range package packing method fan2103mpx -10c to 85c 25-pin molded leadless package (mlp) 5x6 mm tape and reel fan2103empx -40c to 85c 25-pin molded leadless package (mlp) 5x6 mm tape and reel
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 2 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator typical application diagram figure 1. typical application block diagram i ilim current limit comparator gate drive circuit en boot diode error amplifier pwm comparator summing amplifier sw osc ss v ref r s q boot v in gnd v out c boot l c out ilim comp fb ramp v cc ramp gen current sense def level figure 2. block diagram
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 3 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator pin configuration figure 3. mlp 5x6 mm pin configuration (bottom view) pin definitions pin name description p1, 6-12 sw switching node . p2, 2-5 vin power input voltage . connect to the main input power source. p3, 21-23 pgnd power ground . power return and q2 source. 1 boot high-side drive boot voltage . connect through capacitor (c boot ) to sw. the ic includes an internal synchronous bootstrap diode to re charge the capacitor on this pin to v cc when sw is low. 13 pgood power-good flag . an open-drain output that pulls lo w when fb is outside a 10% range of the reference when en is high. pgood does not assert high until the fault latch is enabled. 14 en enable . enables operation when pulled to logic high or left open. toggling en resets the regulator after a latched fault condition. this input has an internal pull-up when the ic is functioning normally. when a latched fault occurs, en is discharged by a current sink. 15 vcc input bias supply for ic . the ic?s logic and analog circuitry are powered from this pin. 16 agnd analog ground . the signal ground for the ic. all internal control voltages are referred to this pin. tie this pin to the ground isl and/plane through the lowe st impedance connection. 17 ilim current limit . a resistor (r ilim ) from this pin to agnd can be used to program the current- limit trip threshold lower than the default setting. 18 r(t) oscillator frequency . a resistor (r t ) from this pin to agnd sets the pwm switching frequency. 19 fb output voltage feedback . connect through a resistor di vider to the output voltage. 20 comp compensation . error amplifier output. connect the ex ternal compensation network between this pin and fb. 24 nc no connect . this pin is not used. 25 ramp ramp amplitude . a resistor (r ramp ) connected from this pin to vin sets the ramp amplitude and provides voltage feedfor ward functionality.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 4 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. parameter conditions min. max. unit vin to pgnd 28 v vcc to agnd agnd = pgnd 6 v boot to pgnd 35 v boot to sw -0.3 6.0 v sw to pgnd transient (t < 20 ns, f < 600 khz) -5 30 v all other pins -0.3 v cc +0.3 v esd human body model, jedec jesd22-a114 2.0 kv charged device model, jedec jesd22-c101 2.5 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. typ. max. unit v cc bias voltage vcc to agnd 4.5 5.0 5.5 v v in supply voltage vin to pgnd 3 24 v t a ambient temperature fan2103m -10 +85 c fan2103em -40 +85 c t j junction temperature +125 c thermal information symbol parameter min. typ. max. unit t stg storage temperature -65 +150 c t l lead soldering temperature, 10 seconds +300 c t vp vapor phase, 60 seconds +215 c t i infrared, 15 seconds +220 c jc thermal resistance: junction-to-case p1 (q2) 4 c/w p2 (q1) 7 c/w p3 4 c/w j-pcb thermal resistance: juncti on-to-mounting surface 35 (1) c/w p d power dissipation, t a = 25c 2.8 (1) w note: 1. typical thermal resistance when mount ed on a four-layer, two-ounce pcb, as shown in figure 26. actual results are dependent on mounting method and surf ace related to the design.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 5 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator electrical specifications recommended operating conditions are the re sult of using the circuit shown in figure 1 unless otherwise noted. parameter conditions min. typ. max. unit power supplies v cc current sw = open, fb = 0.7 v, v cc = 5 v, f sw = 600 khz 8 12 ma shutdown: en = 0, v cc = 5 v 7 10 a v cc uvlo threshold rising v cc 4.1 4.3 4.5 v hysteresis 300 mv oscillator frequency r t = 50 k 255 300 345 khz r t = 24 k 540 600 660 khz minimum on-time (2) 50 65 ns ramp amplitude, pk?pk 16 v in , 1.8 v out , r t = 30 k , r ramp = 200 k 0.53 v minimum off-time (2) 100 150 ns reference reference voltage (v fb ) fan2103m, 25c 794 800 806 mv fan2103em, 25c 795 800 805 mv temperature coefficient fan2103m, -10 to +85c 50 ppm fan2103em, -40 to +85c 70 ppm error amplifier dc gain (2) v cc = 5 v 80 85 db gain bandwidth product (2) 12 15 mhz output voltage (v comp ) 0.4 3.2 v output current, sourcing v cc = 5 v, v comp = 2.2 v 1.5 2.2 ma output current, sinking v cc = 5 v, v comp = 1.2 v 0.8 1.2 ma fb bias current v fb = 0.8 v, 25c -850 -650 -450 na protection and shutdown current limit r ilim open 3.8 5.0 7.0 a i lim current 25c, v cc = 5 v 9 10 11 a over-temperature shutdown internal ic temperature +160 c over-temperature hysteresis +30 c over-voltage threshold 2 cons ecutive clock cycles 110 115 120 %v out under-voltage shutdown 16 consec utive clock cycles 68 73 78 %v out fault discharge threshold measured at fb pin 250 mv fault discharge hysteresis measured at fb pin (v fb ~500 mv) 250 mv soft-start v out to regulation (t0.8) frequency = 600 khz 5.3 ms fault enable/ssok (t1.0) 6.7 ms note: 2. specifications guaranteed by design and characteri zation; not production tested.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 6 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator electrical specifications (continued) recommended operating conditions are the result of using the circuit show n in figure 1 unless otherwise noted. parameter conditions min. typ. max. unit control functions en threshold, rising 1.35 2.00 v en hysteresis 250 mv en pull-up resistance 800 k en discharge current auto-restart mode 1 a fb ok drive resistance 800 pgood threshold (compared to v ref ) fb < v ref -14 -11 -8 %v ref fb > v ref +7 +10 +13 %v ref pgood output low i out < 2 ma 0.4 v
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 7 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator typical characteristics 0.990 0.995 1.000 1.005 1.010 -50 0 50 100 150 temperature ( o c) v fb 0.80 0.90 1.00 1.10 1.20 -50 0 50 100 150 temperature ( o c) i fb figure 4. reference voltage (v fb ) vs. temperature, normalized figure 5. reference bias current (i fb ) vs. temperature, normalized 0 300 600 900 1200 1500 0 20 40 60 80 100 120 140 r t (k ) frequency (khz ) 0.98 0.99 1.00 1.01 1.02 -50 0 50 100 150 temperature ( o c) frequency figure 6. frequency vs. r t figure 7. frequency vs. temperature, normalized 0.60 0.80 1.00 1.20 1.40 1.60 -50 0 50 100 15 0 temperature ( o c) r ds 0.96 0.98 1.00 1.02 1.04 -50 0 50 100 150 temperature ( o c) i ilim figure 8. r ds vs. temperature, normalized (v cc = v gs = 5 v) figure 9. i lim current (i ilim ) vs. temperature, normalized q1 ~0.32 %/ o c q2 ~0.35 %/ o c 300khz 600khz
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 8 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator application circuit sw p1 pgnd p3 v out p2 vin boot 1 comp vcc pgood 8-20 v in en +5v agnd ramp 20 15 25 13 14 16 18 r(t) 17 ilim 24 19 fb nc v out 2x4.7 *tdk rlf7030t-3r3m4r1 390p 1.5w 4x22 3.3n 200k 200k 2. 00k 30.1k 4. 7n 1.0 10k 2.49k 2.49k 56p 4.7n 62 4.7n 0.1 3.3 * x5r x7r x5r figure 10. application circuit: 1.8 v out , 500 khz typical performance characteristics typical operating characteristics usi ng the circuit shown in figure 10. v in =16 v, v cc =5 v, unless otherwise specified. efficiency 55 60 65 70 75 80 85 90 95 100 0.00 0.50 1.00 1.50 2.00 2.50 3.00 load current (a) efficiency (%) effi12v (%) effi8v (%) effi18v (%) power loss 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 load current (a) loss (w) loss12v (w) loss8v (w) loss18v (w) figure 11. 1.8 v out efficiency over v in vs. load figure 12. 1.8 v out dissipation over v in vs. load regulation characteristic 1.818 1.820 1.822 1.824 1.826 1.828 0.00 0.50 1.00 1.50 2.00 2.50 3.00 load current (a) vo (v) vo8v (v) vo12v (v) vo18v (v) 65 70 75 80 85 90 95 100 0.00 0.50 1.00 1.50 2.00 2.50 3.00 load current (a) efficiency efficiency (%) v in =8v , 300khz v in =12v , 500khz figure 13. 1.8 v out regulation vs. load figure 14. 3.3 v out efficiency vs. load (circuit values changed)
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 9 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator typical performance characteristics (continued) typical operating characteristics usi ng the circuit shown in figure 10. v in =12 v, v cc =5 v, unless otherwise specified. figure 15. sw and v out ripple, 3 a load figure 16. startup with 1 v pre-bias on v out figure 17. transient response, 1.5-3 a load (circuit values changed) figure 18. re-start on fault figure 19. startup, 3 a load figure 20. shutdown, 3 a load
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 10 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator circuit description initialization once v cc exceeds the uvlo threshold and en is high, the ic checks for an open or shorted fb pin before releasing the internal soft-start ramp (ss). if r1 is open (as shown in figure 1), the error amplifier output (comp) is forc ed low and no pulses are generated. after the ss ramp times out (t1.0), an under- voltage latched fault occurs. if the parallel combination of r1 and r bias is 1k , the internal ss ramp is not re leased and the regulator does not start. soft-start once internal ss ramp has charged to 0.8 v (t0.8), the output voltage is in regulati on. until ss ramp reaches 1.0 v (t1.0), the ?fault latch? is inhibited. to avoid skipping the soft-start cycle, it is necessary to apply v in before v cc reaches its uvlo threshold. soft-start time is a function of oscillator frequency. ss 1.35v fb en 0.8v t0.8 t1.0 3200 clks 4000 clks fault latc h enable 0.8v 1.0v 2400 clks figure 21. soft-start timing diagram the regulator does not allow the low-side mosfet to operate in full synchronous rectification mode until internal ss ramp reaches 95% of v ref (~0.76 v). this helps the regulator start against pre-biased outputs (as shown in figure 16) and ensur es that inductor current does not "ratchet" up during the soft-start cycle. v cc uvlo or toggling the en pin discharges the ss and resets the ic. bias supply the fan2103 requires a 5 v supply rail to bias the ic and provide gate-drive ener gy and controller power. connect a 1.0 f x5r or x7 r decoupling capacitor between vcc and pgnd. whenev er the en pin is pulled up to v cc , the 5 v supply connected to v cc should be turned on after v in comes up. if the power supply is turned on using en pin with an external control after v cc and v in come up, the v cc and v in power sequencing is not relevant. since v cc is used to drive the internal mosfet gates, supply current is frequency and voltage dependent. approximate v cc current (i cc ) can be calculated using: )] 128 f ( ) 013 . 0 227 5 v [( 58 . 4 i cc ) ma ( cc ? ? + ? + = (1) where frequency (f) is expressed in khz. setting the output voltage the output voltage of the r egulator can be set from 0.8 v to ~80% of v in by an external resistor divider (r1 and r bias in figure 1). the internal reference is 0.8 v with 650 na, sourced from the fb pin to ensure t hat if the pi n is open, the regulator does not start. the external resistor divider is calculated using: na 650 1 r v 8 . 0 v r v 8 . 0 out bias + ? = (2) connect r bias between fb and agnd. setting the frequency oscillator frequency is determined by an external resistor, r t, connected between the r(t) pin and agnd: 135 ) r 65 ( 10 f t 6 ) khz ( + ? = (3) where r t is expressed in k . 65 135 ) f / 10 ( r 6 ) k ( t ? = (4) where frequency (f) is expressed in khz. the regulator does not start if r t is left open.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 11 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator calculating the inductor value typically the inductor is set for a ripple current ( i l ) of 10% to 35% of the maximum dc load. regulators requiring fast transient response use a value on the high side of this range, while regulators that require very low output ripple and/or use high-esr capacitors restrict allowable ripple current: f l d) - (1 v out ? ? = l i (5) where f is the oscillator frequency and: f d) - (1 v out ? ? = l i l (6) setting the ramp resistor value the internal ramp voltage excursion ( ? v ramp ) during t on should be set to 0.6 v. r ramp is approximately: 2 f v 10 x 18 v ) 8 . 1 v ( r in 6 out in ) k ( ramp ? ? ? ? ? = ? (7) where frequency (f) is expressed in khz. setting the current limit the current limit system involves two comparators. the max i limit comparator is used with a v ilim fixed-voltage reference and represents the maximum current limit allowable. this reference voltage is temperature compensated to reflect the r dson variation of the low- side mosfet. the adjust i limit comparator is used where the current limit needs to be set lower than the v ilim fixed reference. the 10 a current source does not track the r dson changes over temperature, so change is added into the equations for calculating the adjust i limit comparator reference voltage, as is shown below. figure 22 shows a simplified schematic of the over- current system. figure 22. current-limit system schematic since the i lim voltage is set by a 10 a current source into the r ilim resistor, the basic equation for setting the reference voltage is: v rilim = 10a*r ilim (8) to calculate r ilim : r ilim = v rilim / 10a (9) the voltage v rilim is made up of two components, v bot (which relates to the current through the low-side mosfet) and v rmpeak (which relates to the peak current through the inductor). combining those two voltage terms results in: r ilim = (v bot + v rmpeak )/ 10a (10) r ilim = {0.96 + (i load * r dson *k t *8)} + {d*(v in ? 1.8)/(f sw *0.03*r ramp )}/10a (11) where: v bot = 0.96 + (i load * r dson *k t *8); v rmpeak = d*(v in ? 1.8)/(f sw *0.03*r ramp ); i load = the desired maximum load current; r dson = the nominal r dson of the low-side mosfet; k t = the normalized temperature coefficient for the low-side mosfet (on datasheet graph); d = v out /v in duty cycle; f sw = clock frequency in khz; and r ramp = chosen ramp resistor value in k . after 16 consecutive, pulse-by-pulse, current-limit cycles, the fault latch is set and the regulator shuts down. cycling v cc or en restores operation after a normal soft-start cycle (refer to the auto-restart section) . the over-current protection fault latch is active during the soft-start cycle. use 1% resistor for r ilim . loop compensation the loop is compensated using a feedback network around the error amplifier. figure 23 shows a complete type-3 compensation network. type-2 compensation eliminates r3 and c3. figure 23. compensation network + _ v cc 1 0a ilimit ilim rilim + _ ilimit adjust max + _ comp pwm verr pwm ilimtrip vilim ramp
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 12 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator because the fan2103 employs summing current-mode architecture, type-2 compensation can be used for many applications. for applications that require wide loop bandwidth and/or use very low-esr output capacitors, type-3 compensation may be required. r ramp provides feedforward compensation for changes in v in . with a fixed r ramp value, the modulator gain increases as v in is reduced, which could make it difficult to compensate the loop. for designs with low input voltages (3 v to 6.5 v), it is recommended that a separate r ramp and the compensation component values are used as compared to designs with v in between 6.5 v and 24 v. protection the converter output is m onitored and protected against extreme overload, short-ci rcuit, over-voltage, and under- voltage conditions. an internal ?fault latch? is set for any fault intended to shut down the ic. when the fault latch is set, the ic discharges v out by enhancing the low-side mosfet until fb<0.25 v. the mosfet is not turned on again unless fb>0.5 v. this behavior discharges the output without causing undershoot (negative output voltage). gate drive pwm 0.25/0.5v fault pwm latch fb figure 24. latched fault response under-voltage shutdown if fb remains below the under-voltage threshold for 16 consecutive clock cycles, the fault latch is set and the converter shuts down. this fault is prevented from setting the fault latch during soft-start. over-voltage protection / shutdown if fb exceeds 115% ? v ref for two consecutive clock cycles, the fault latch is set and shutdown occurs. a shorted high-side mosfet condition is detected when sw voltage exceeds ~0.7 v while the low-side mosfet is fully enhanced. the fault latch is set immediately upon detection. the two fault protection circuits above are active all the time, including during soft-start. auto-restart after a fault, en is discharged with 1 a to a 1.1 v threshold before the 800 k pull-up is restored. a new soft-start cycle begins when en charges above 1.35 v. depending on the external circuit, the fan2103 can be provisioned to remain latched-off or automatically restart after a fault. table 1. fault / restart provisioning en pin controller / restart state pull to gnd off (disabled) v cc no restart ? latched off (after v cc comes up) open immediate restart after fault cap to gnd new soft-start cycle after: t delay (ms) = 3.9 ? c(nf) with en left open, restart is immediate. if auto-restart is not desired, tie the en pin to the vcc pin or pull it high after v cc comes up with a logic gate to keep the 1 a current sink from discharging en to 1.1 v. figure 25. fault latch with delayed auto-restart over-temperature protection fan2103 incorporates an ov er-temperature protection circuit that sets the fault latch when a die temperature of about 160c is reached. the ic is allowed to restart when the die temperature falls below 130c. power good (pgood) signal pgood is an open-drain output that asserts low when v out is out of regulation, as measured at the fb pin (thresholds are specified in t he electrical specifications section). pgood does not a ssert high until the fault latch is enabled (t1.0). pcb layout figure 26. recommended pcb layout
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 13 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator physical dimensions a) dimensions are in millimeters. b) dimensions and tolerances per asme y14.5m, 1994 top view bottom view recommended land pattern 2x 2x side view seating plane c) dimensions do not include mold flash or burrs. f) drawing filename: mkt-mlp25arev3 d) design based on jedec mo-220 variation wjhc all values typical except where noted e) terminals are symmetrical around the x & y axis except where depopulated. optional lead design (leads# 1, 24 & 25 only) scale: 1.5x figure 27. 5x6 mm molded leadless package (mlp) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com fan2103 ? rev. 1.0.8 14 fan2103 ? tinybuck? 3 a, 24 v input, integrated synchronous buck regulator

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